R
Functional Description
Flash PROM, as illustrated in Figure 51. The FPGA sup-
plies the CCLK output clock from its internal oscillator to the
attached Platform Flash PROM. In response, the Platform
Flash PROM supplies bit-serial data to the FPGA’s DIN
input, and the FPGA accepts this data on each rising CCLK
edge.
Master Serial Mode
For additional information, refer to the Master Serial Mode
chapter in UG332.
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
OE/RESET
+2.5V
Platform Flash
Spartan-3E
FPGA
XCFxx
CE
CF
CEO
+2.5V
JTAG
VCCAUX
TDO
+2.5V
VCCJ
TDO
+2.5V
TDI
TDI
TDI
TMS
TCK
TDO
TMS
TCK
TMS
TCK
GND
PROG_B
DONE
GND
PROG_B
Recommend
open-drain
driver
DS312-2_44_082009
Figure 51: Master Serial Mode using Platform Flash PROM
All mode select pins, M[2:0], must be Low when sampled,
when the FPGA’s INIT_B output goes High. After configura-
tion, when the FPGA’s DONE output goes High, the mode
select pins are available as full-featured user-I/O pins.
FPGA configuration. After configuration, when the FPGA’s
DONE output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
P
Similarly, the FPGA’s HSWAP pin must be Low to
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the con-
figuration process.
enable pull-up resistors on all user-I/O pins during configu-
ration or High to disable the pull-up resistors. The HSWAP
control must remain at a constant logic level throughout
72
www.xilinx.com
DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
