R
Functional Description
Table 46: Pin Behavior during Configuration (Continued)
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
Slave
Parallel
Pin Name
D1
Master Serial
JTAG
Slave Serial
I/O Bank(3)
D1
D0
D1
D0
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D0/DIN
RDWR_B
A23
DIN
DIN
DIN
RDWR_B
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
RDWR_B
A22
A21
A20
A19/VS2
A18/VS1
A17/VS0
A16
VS2
VS1
VS0
A15
A14
A13
A12
A11
A10
A9
A8
A8
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
LDC0
LDC1
LDC2
HDC
LDC0
LDC1
LDC2
HDC
Notes:
1. Gray shaded cells represent pins that are in a high-impedance state (Hi-Z, floating) during configuration. These pins have an optional
internal pull-up resistor to their respective VCCO supply pin that is active throughout configuration if the HSWAP input is Low.
2. Yellow shaded cells represent pins with an internal pull-up resistor to its respective voltage supply rail that is active during
configuration, regardless of the HSWAP pin.
3. Note that dual-purpose outputs are supplied by VCCO, and configuration inputs are supplied by VCCAUX
.
Table 47: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard
Output Drive
Slew Rate
All, including CCLK
LVCMOS25
8 mA
Slow
The HSWAP pin itself has an pull-up resistor enabled during
configuration. However, the VCCO_0 supply voltage must
be applied before the pull-up resistor becomes active. If the
VCCO_0 supply ramps after the VCCO_2 power supply, do
not let HSWAP float; tie HSWAP to the desired logic level
externally.
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
DS312-2 (v3.8) August 26, 2009
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Product Specification
XILINX [ XILINX, INC ]
