R
Functional Description
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK. All
other configuration pins are dual-purpose I/O pins and are
available to the FPGA application after the DONE pin goes
High. See Start-Up for additional information.
In the Master Serial, SPI, and BPI configuration modes, the
FPGA drives the CCLK pin and CCLK should be treated as
a full bidirectional I/O pin for signal integrity analysis. In BPI
mode, CCLK is only used in multi-FPGA daisy-chains.
The best signal integrity is ensured by following these basic
PCB guidelines:
Table 47 shows the default I/O standard setting for the vari-
ous configuration pins during the configuration process. The
configuration interface is designed primarily for 2.5V opera-
tion when the VCCO_2 (and VCCO_1 in BPI mode) con-
nects to 2.5V.
•
•
•
•
Route the CCLK signal as a 50 Ω
controlled-impedance transmission line.
Route the CCLK signal without any branching. Do not
use a “star” topology.
Keep stubs, if required, shorter than 10 mm (0.4
inches).
The configuration pins also operate at other voltages by set-
ting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or
1.8V. The change on the V
supply also changes the I/O
CCO
characteristics, including the effective IOSTANDARD. For
example, with V = 3.3V, the output characteristics will
Terminate the end of the CCLK transmission line.
CCO
be similar to those of LVCMOS33, and the current when
driving High, I , increases to approximately 12 to 16 mA,
Design Considerations for the HSWAP, M[2:0],
and VS[2:0] Pins
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
OH
while the current when driving Low, I , remains 8 mA. At
OL
V
= 1.8V, the output characteristics will be similar to
CCO
those of LVCMOS18, and the current when driving High,
, decreases slightly to approximately 6 to 8 mA. Again,
I
Unlike previous Spartan FPGA families, nearly all of the
Spartan-3E dual-purpose configuration pins are available
as full-featured user I/O pins after successful configuration,
when the DONE output goes High.
OH
the current when driving Low, I , remains 8 mA. The out-
OL
put voltages are determined by the V
level, LVCMOS18
CCO
for 1.8V, LVCMOS25 for 2.5V, and LVCMOS33 for 3.3V. For
more details see UG332.
The HSWAP pin, the mode select pins (M[2:0]), and the
variant-select pins (VS[2:0]) must have valid and stable
logic values at the start of configuration. VS[2:0] are only
used in the SPI configuration mode. The levels on the
M[2:0] pins and VS[2:0] pins are sampled when the INIT_B
pin returns High. See Figure 77 for a timing example.
CCLK Design Considerations
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
The FPGA’s configuration process is controlled by the
CCLK configuration clock. Consequently, signal integrity of
CCLK is important to guarantee successful configuration.
Poor CCLK signal integrity caused by ringing or reflections
might cause double-clocking, causing the configuration pro-
cess to fail.
The HSWAP pin defines whether FPGA user I/O pins have
a pull-up resistor connected to their associated V
sup-
CCO
ply pin during configuration or not, as shown Table 48.
HSWAP must be valid at the start of configuration and
remain constant throughout the configuration process.
Although the CCLK frequency is relatively low, Spartan-3E
FPGA output edge rates are fast. Therefore, careful atten-
tion must be paid to the CCLK signal integrity on the printed
circuit board. Signal integrity simulation with IBIS is recom-
mended. For all configuration modes except JTAG, the sig-
nal integrity must be considered at every CCLK trace
destination, including the FPGA’s CCLK pin.
Table 48: HSWAP Behavior
HSWAP
Value
Description
0
Pull-up resistors connect to the associated
V
supply for all user-I/O or dual-purpose
CCO
I/O pins during configuration. Pull-up resistors
are active until configuration completes.
This analysis is especially important when the FPGA
re-uses the CCLK pin as a user-I/O after configuration. In
these cases, there might be unrelated devices attached to
CCLK, which add additional trace length and signal destina-
tions.
1
Pull-up resistors disabled during configuration.
All user-I/O or dual-purpose I/O pins are in a
high-impedance state.
70
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DS312-2 (v3.8) August 26, 2009
Product Specification
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