R
Functional Description
CCLK
+1.2V
+1.2V
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCINT
VCCINT
P
HSWAP
VCCO_0
VCCO_0
P
HSWAP
VCCO_0
VCCO_0
VCCINT
VCCO_2
DIN
V
VCCO_2
V
Slave
Serial
Mode
D0
VCCO
V
Serial Master
Mode
CCLK
DOUT
INIT_B
CLK
‘0’
‘0’
‘0’
M2
M1
M0
‘1’
‘1’
‘1’
M2
M1
M0
DOUT
INIT_B
DOUT
OE/RESET
Platform Flash
Spartan-3E
FPGA
Spartan-3E
FPGA
XCFxx
CE
CF
CEO
CCLK
DIN
+2.5V
JTAG
VCCAUX
+2.5V
VCCJ
TDO
+2.5V
VCCAUX
+2.5V
TDI
TDI
TDO
TDI
TDI
TDO
TMS
TCK
TDO
TMS
TCK
TMS
TCK
TMS
TCK
V
+2.5V
GND
PROG_B
DONE
PROG_B
DONE
GND
GND
PROG_B
PROG_B
Recommend
open-drain
driver
TCK
TMS
DONE
INIT_B
DS312-2_45_082009
Figure 52: Daisy-Chaining from Master Serial Mode
provided by the Xilinx iMPACT programming software and
the associated Xilinx Parallel Cable IV or Platform Cable
USB programming cables.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 52. Use Master Serial mode
(M[2:0] = <0:0:0>) for the FPGA connected to the Platform
Flash PROM and Slave Serial mode (M[2:0] = <1:1:1>) for
all other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the Platform Flash, the mas-
ter device supplies data using its DOUT output pin to the
next device in the daisy-chain, on the falling CCLK edge.
Storing Additional User Data in Platform Flash
After configuration, the FPGA application can continue to
use the Master Serial interface pins to communicate with
the Platform Flash PROM. If desired, use a larger Platform
Flash PROM to hold additional non-volatile application data,
such as MicroBlaze processor code, or other user data such
as serial numbers and Ethernet MAC IDs. The FPGA first
configures from Platform Flash PROM. Then using FPGA
logic after configuration, the FPGA copies MicroBlaze code
from Platform Flash into external DDR SDRAM for code
execution.
JTAG Interface
Both the Spartan-3E FPGA and the Platform Flash PROM
have a four-wire IEEE 1149.1/1532 JTAG port. Both devices
share the TCK clock input and the TMS mode select input.
The devices may connect in either order on the JTAG chain
with the TDO output of one device feeding the TDI input of
the following device in the chain. The TDO output of the last
device in the JTAG chain drives the JTAG connector.
See XAPP694: Reading User Data from Configuration
PROMs and XAPP482: MicroBlaze Platform Flash/PROM
Boot Loader and User Data Storage for specific details on
how to implement such an interface.
SPI Serial Flash Mode
The JTAG interface on Spartan-3E FPGAs is powered by
For additional information, refer to the “Master SPI Mode”
chapter in UG332.
the 2.5V V
supply. Consequently, the PROM’s V
CCAUX
CCJ
supply input must also be 2.5V. To create a 3.3V JTAG inter-
face, please refer to application note XAPP453: The 3.3V
Configuration of Spartan-3 FPGAs for additional informa-
tion.
In SPI Serial Flash mode (M[2:0] = <0:0:1>), the Spartan-3E
FPGA configures itself from an attached industry-standard
SPI serial Flash PROM, as illustrated in Figure 53 and
Figure 54. The FPGA supplies the CCLK output clock from
its internal oscillator to the clock input of the attached SPI
Flash PROM.
In-System Programming Support
Both the FPGA and the Platform Flash PROM are in-system
programmable via the JTAG chain. Download support is
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
75
Product Specification
XILINX [ XILINX, INC ]
