R
Functional Description
Table 46 shows how various pins behave during the FPGA
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
Configuration Bitstream Image Sizes
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in Table 45. The configuration file size for a
multiple-FPGA daisy-chain design roughly equals the sum
of the individual file sizes.
Table 45: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
All user-I/O pins, input-only pins, and dual-purpose pins that
are not actively involved in the currently-select configuration
mode are high impedance (floating, three-stated, Hi-Z) dur-
ing the configuration process. These pins are indicated in
Table 46 as gray shaded table entries or cells.
Number of
Spartan-3E FPGA
XC3S100E
Configuration Bits
581,344
The HSWAP input controls whether all user-I/O pins,
input-only pins, and dual-purpose pins have a pull-up resis-
tor to the supply rail or not. When HSWAP is Low, each pin
has an internal pull-up resistor that is active throughout con-
figuration. After configuration, pull-up and pull-down resis-
tors are available in the FPGA application as described in
Pull-Up and Pull-Down Resistors.
XC3S250E
1,353,728
XC3S500E
2,270,208
XC3S1200E
XC3S1600E
3,841,184
5,969,696
The yellow-shaded table entries or cells represent pins
where the pull-up resistor is always enabled during configu-
ration, regardless of the HSWAP input. The post-configura-
tion behavior of these pins is defined by Bitstream
Generator options as defined in Table 69.
Pin Behavior During Configuration
For additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
Table 46: Pin Behavior during Configuration
SPI (Serial
Flash)
BPI (Parallel
NOR Flash)
Slave
Parallel
Pin Name
Master Serial
JTAG
Slave Serial
I/O Bank(3)
IO* (user-I/O)
-
IP* (input-only)
TDI
TMS
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
0
TDI
TMS
TCK
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
TDI
TMS
TCK
TDO
PROG_B
DONE
HSWAP
1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
0
TCK
TDO
TDO
PROG_B
DONE
HSWAP
M2
PROG_B
DONE
HSWAP
0
2
M1
0
0
1
0
1
1
2
M0
0
1
0 = Up
1
0
1
2
1 = Down
CCLK
INIT_B
CSO_B
DOUT/BUSY
MOSI/CSI_B
D7
CCLK (I/O)
INIT_B
CCLK (I/O)
INIT_B
CSO_B
DOUT
CCLK (I/O)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
CSO_B
BUSY
CSI_B
D7
CCLK (I)
INIT_B
2
2
2
2
2
2
2
2
2
2
2
DOUT
DOUT
MOSI
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
68
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DS312-2 (v3.8) August 26, 2009
Product Specification
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