R
Functional Description
SelectIO Signal Standards
Q
Q
D
D
D1
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards (Table 6 and
Table 7). The majority of the I/Os also can be used to form
differential pairs to support any of the differential signaling
standards (Table 7).
PAD
From
Fabric
D2
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to the Xilinx Software Manuals and
Help.
OCLK1
OCLK2
OCLK1
OCLK2
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. For a
d
particular V
voltage, Table 6 and Table 7 list all of the
D1
D2
d+2
d+4
d+6
d+8
d+10
d+9
CCO
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
d+1
d+3
d+5
d+7
d+5 d+6
d+8
PAD
d+7
d
d+1 d+2 d+3 d+4
DS312-2_23_030105
Figure 10: Output DDR
Table 6: Single-Ended IOSTANDARD Bank Compatibility
Supply/Compatibility
V
Input Requirements
Board
CCO
Single-Ended
IOSTANDARD
Termination
1.2V
1.5V
1.8V
2.5V
3.3V
V
Voltage (V )
REF
TT
Input/
Output
(1)
LVTTL
-
-
-
-
N/R
N/R
Input/
Output
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
-
-
-
-
-
-
-
-
-
-
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
Input/
Output
Input
Input
Input
Input
N/R
N/R
N/R
Input/
Output
Input
Input
Input
-
Input/
Output
Input
Input/
Output
(1)
Input
Input
N/R
Input/
Output
-
-
-
-
-
-
-
-
-
-
N/R
N/R
0.9
Input/
Output
PCI66_3
-
Input/
Output
HSTL_I_18
HSTL_III_18
Input
Input
Input
Input
Input/
Output
1.1
1.8
16
www.xilinx.com
DS312-2 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
