R
DC and Switching Characteristics
All Speed Grades
Table 117: Timing for the Slave Parallel Configuration Mode (Continued)
Symbol
Description
Min
Max
Units
Hold Times
T
T
T
The time from the active edge of the CCLK pin to the point when data is last
held at the D0-D7 pins
1.0
0
-
-
-
ns
ns
ns
SMCCD
SMCCCS
SMWCC
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the CSO_B pin
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the RDWR_B pin
0
Clock Timing
T
T
F
The High pulse width at the CCLK input pin
5
5
0
0
0
-
ns
CCH
The Low pulse width at the CCLK input pin
-
ns
CCL
(2)
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin
Using the BUSY pin
50
66
20
MHz
MHz
MHz
CCPAR
With bitstream compression
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 77.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
DS312-3 (v3.8) August 26, 2009
www.xilinx.com
155
Product Specification
XILINX [ XILINX, INC ]
