R
DC and Switching Characteristics
Slave Parallel Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CSI_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input)
1/FCCPAR
Byte n
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n+1
TSMCKBY
TSMCKBY
High-Z
High-Z
BUSY
(Output)
BUSY
DS312-3_02_103105
Notes:
1. It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 76: Waveforms for Slave Parallel Configuration
Table 117: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max
Units
Clock-to-Output Times
T
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
-
12.0
ns
SMCKBY
Setup Times
T
The time from the setup of data at the D0-D7 pins to the active edge the CCLK
pin
11.0
-
ns
SMDCC
T
T
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
10.0
23.0
-
-
ns
ns
SMCSCC
(2)
SMCCW
154
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DS312-3 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
