Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 47: Global Clock Switching Characteristics
Speed Grade
Symbol
Description
Devices
Units
-4
-3
-2
-1L
0.60
N/A
TGSI
S pin Setup to I0/I1 inputs LX Family
LXT Family
N/A
0.25
N/A
0.21
0.31
0.31
0.21
0.21
0.48
0.48
0.21
0.21
ns
ns
ns
ns
LX Family
BUFGMUX delay from
I0/I1 to O
TGIO
LXT Family
N/A
N/A
Maximum Frequency
LX Family
Global clock tree (BUFG)
LXT Family
N/A
400
400
400
375
375
MHz
MHz
FMAX
Table 48: Input/Output Clock Switching Characteristics (BUFIO2)
Speed Grade
Symbol
TBUFCKO_O
Description
Devices
Units
-4
-3
-2
-1L
1.80
N/A
Clock to out delay from I to O
LX Family
N/A
0.67
0.82
0.82
1.09
1.09
ns
ns
LXT Family
Maximum Frequency
FMAX
I/O clock tree (BUFIO2)
LX Family
N/A
540
525
525
500
500
MHz
MHz
LXT Family
N/A
Table 49: Input/Output Clock Switching Characteristics (BUFPLL)
Speed Grade
Symbol
Description
Devices
Units
-4
-3
-2
-1L
Maximum Frequency
FMAX
BUFPLL clock tree (BUFPLL) LX Family
LXT Family
N/A
1050
1050
950
950
MHz
MHz
1080
N/A
DS162 (v1.9) August 23, 2010
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Advance Product Specification
47
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