Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 50: PLL Specification
Speed Grade
(1)
Symbol
Description
Device
Units
-4
-3
-2
-1L
N/A
N/A
N/A
FINMAX
Maximum Input Clock Frequency
from I/O Clock
LX Family
LXT Family
LX Family
LXT Family
LX Family
LXT Family
All
N/A
540
N/A
400
N/A
19
525
525
400
400
19
450
450
375
375
19
MHz
MHz
MHz
MHz
MHz
MHz
Maximum Input Clock Frequency
from Global Clock
FINMIN
Minimum Input Clock Frequency
19
19
FINJITTER
FINDUTY
Maximum Input Clock Period Jitter
<20% of clock input period or 1 ns Max
Allowable Input Duty Cycle: 19—199 MHz All
Allowable Input Duty Cycle: 200—299 MHz All
25/75
35/65
45/55
%
%
Allowable Input Duty Cycle: > 300 MHz
Minimum PLL VCO Frequency
All
%
FVCOMIN
LX Family
LXT Family
LX Family
LXT Family
All
N/A
400
N/A
1080
1
400
400
400
400
1000
1000
1
400
N/A
1000
N/A
1
MHz
MHz
MHz
MHz
MHz
MHz
ns
FVCOMAX
Maximum PLL VCO Frequency
1050
1050
1
FBANDWIDTH
Low PLL Bandwidth at Typical(3)
High PLL Bandwidth at Typical(3)
Static Phase Offset of the PLL Outputs
PLL Output Jitter(3)
All
4
4
4
4
TSTAPHAOFFSET
TOUTJITTER
TOUTDUTY
All
0.12
0.12
0.12
Note 2
0.20
100
375
375
950
950
3.125
All
PLL Output Clock Duty Cycle Precision(4) All
0.15
100
0.15
100
ns
TLOCKMAX
PLL Maximum Lock Time
All
100
N/A
µs
LX Family
LXT Family
LX Family
LXT Family
All
N/A
400
MHz
MHz
MHz
MHz
MHz
PLL Maximum Output Frequency for
BUFGMUX
FOUTMAX
400
400
N/A
1050
1050
3.125
PLL Maximum Output Frequency for
BUFPLL
FOUTMAX
1080
3.125
N/A
FOUTMIN
PLL Minimum Output Frequency(5)
External Clock Feedback Variation
Minimum Reset Pulse Width
3.125
TEXTFDVAR
RSTMINPULSE
All
< 20% of clock input period or 1 ns Max
All
5
5
5
5
ns
(5)
FPFDMAX
Maximum Frequency at the Phase
Frequency Detector
LX Family
LXT Family
LX Family
LXT Family
All
N/A
500
N/A
19
500
500
19
400
400
19
MHz
MHz
MHz
MHz
N/A
FPFDMIN
Minimum Frequency at the Phase
Frequency Detector
19
19
N/A
TFBDELAY
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
Notes:
1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade.
2. Values for this parameter are available in the Clocking Wizard.
3. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
4. Includes global clock buffer.
5. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
6. When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector
frequency. F = F / CLKFBOUT_MULT
PFDMAX
CLKFB
DS162 (v1.9) August 23, 2010
Advance Product Specification
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