R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (cont.)
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
-5
-4
Symbol
Dual Port RAM
Size
Min Max Min Max Units
Write Operation(1)
TWCDS
TWPDS
TASDS
TDSDS
TWSDS
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
7.7
3.1
1.3
1.7
1.4
0
-
8.4
3.6
1.5
2.0
1.6
0
-
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
TWODS
Data valid after clock K
-
5.2
-
6.1
Notes:
1. Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
Dual Port
TWPS
TWPDS
WCLK (K)
WCLK (K)
TWSS
TWHS
TWSDS
TWHDS
WE
WE
TDHS
TDHDS
TDSS
TDSDS
DATA IN
DATA IN
TAHS
TASS
TAHDS
TASDS
ADDRESS
DATA OUT
ADDRESS
DATA OUT
TILO
TILO
TILO
TILO
TWODS
OLD
TWOS
OLD
NEW
NEW
DS060_34_011300
DS060 (v1.8) June 26, 2008
www.xilinx.com
57
Product Specification
XILINX [ XILINX, INC ]
