R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and expressed in nanoseconds unless otherwise noted.
Speed Grade
-5
-4
Symbol
Clocks
TCH
Description
Min
Max
Min
Max
Units
Clock High time
Clock Low time
2.0
2.0
-
-
2.3
2.3
-
-
ns
ns
TCL
Combinatorial Delays
TILO
TIHO
F/G inputs to X/Y outputs
-
-
-
-
1.0
1.7
1.5
1.5
-
-
-
-
1.1
2.0
1.8
1.8
ns
ns
ns
ns
F/G inputs via H to X/Y outputs
TITO
F/G inputs via transparent latch to Q outputs
C inputs via H1 via H to X/Y outputs
THH1O
Sequential Delays
TCKO
Clock K to Flip-Flop or latch outputs Q
-
1.2
-
1.4
ns
Setup Time before Clock K
TICK
F/G inputs
0.6
1.3
-
-
0.7
1.6
-
-
ns
ns
TIHCK
F/G inputs via H
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
TRPW Width (High)
TRIO Delay from C inputs via S/R, going High to Q
Global Set/Reset
0.0
-
0.0
-
ns
2.5
-
-
2.8
-
-
ns
ns
2.3
2.7
TMRW
TMRQ
FTOG
Minimum GSR Pulse Width
10.5
-
11.5
-
ns
Delay from GSR input to any Q
See page 60 for TRRI values per device.
250 217
Toggle Frequency (MHz)
-
-
MHz
(for export control purposes)
DS060 (v1.8) June 26, 2008
www.xilinx.com
55
Product Specification
XILINX [ XILINX, INC ]
