R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
Speed Grade
-5
Max
1.4
1.7
2.0
2.3
2.6
-4
Max
1.5
1.8
2.1
2.5
2.8
Symbol
Description
Device
Units
ns
TGLS
From pad through buffer, to any clock K
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
ns
ns
ns
ns
54
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DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
