R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan-XL devices
and are expressed in nanoseconds unless otherwise noted.
Speed Grade
-5
-4
Symbol
Single Port RAM
Size(1)
Min
Max
Min
Max
Units
Write Operation
TWCS
TWCTS
TWPS
TWPTS
TASS
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
7.7
7.7
3.1
3.1
1.3
1.5
1.5
1.8
1.4
1.3
0.0
-
-
8.4
8.4
3.6
3.6
1.5
1.7
1.7
2.1
1.6
1.5
0.0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
TASTS
TDSS
-
-
-
-
TDSTS
TWSS
TWSTS
-
-
-
-
WE setup time before clock K
-
-
All hold times after clock K
Data valid after clock K
-
-
TWOS
4.5
5.4
5.3
6.3
TWOTS
-
-
Read Operation
TRC
TRCT
TILO
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
-
3.1
5.5
-
-
-
ns
ns
ns
ns
ns
ns
Data Valid after address change (no Write
Enable)
1.0
1.7
-
1.1
2.0
-
TIHO
TICK
TIHCK
-
-
Address setup time before clock K
0.6
1.3
0.7
1.6
-
-
Notes:
1. Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
