R
Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Speed Grade
-5
-4
Symbol
Description
Device
Min
Max
Min
Max Units
Setup Times
TECIK
TPICK
Clock Enable (EC) to Clock (IK)
All devices
All devices
All devices
0.0
1.0
0.7
-
-
-
0.0
1.2
0.8
-
-
-
ns
ns
ns
Pad to Clock (IK), no delay
TPOCK
Pad to Fast Capture Latch Enable (OK), no delay
Hold Times
All Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays
TPID
TPLI
Pad to I1, I2
All devices
All devices
All devices
All devices
-
-
-
-
0.9
2.1
1.0
1.1
-
-
-
-
1.1
2.5
1.1
1.2
ns
ns
ns
ns
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
TIKRI
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
Delay Adder for Input with Full Delay Option
TDelay
TPICKD = TPICK + TDelay
TPDLI = TPLI + TDelay
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.0
4.8
5.0
5.5
6.5
-
-
-
-
-
4.7
5.6
5.9
6.5
7.6
-
-
-
-
-
ns
ns
ns
ns
ns
Global Set/Reset
TMRW Minimum GSR pulse width
TRRI Delay from GSR input to any Q
All devices 10.5
-
11.5
-
ns
ns
ns
ns
ns
ns
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
-
-
-
-
-
9.0
-
-
-
-
-
10.5
11.0
11.5
12.5
13.5
9.5
10.0
11.0
12.0
Notes:
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
60
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DS060 (v1.8) June 26, 2008
Product Specification
XILINX [ XILINX, INC ]
