R
Virtex-II Platform FPGAs: Pinout Information
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
IO_L96N_2
Pin Number
No Connect in the XC2V40
2
2
G11
G13
IO_L96P_2
3
3
3
3
3
3
3
3
3
3
IO_L96N_3
IO_L96P_3
G12
H12
H11
J13
J10
K13
K12
K11
K10
L13
IO_L94N_3
IO_L94P_3
IO_L03N_3/VREF_3
IO_L03P_3
IO_L02N_3/VRP_3
IO_L02P_3/VRN_3
IO_L01N_3
IO_L01P_3
(1)
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01N_4/BUSY/DOUT
IO_L01P_4/INIT_B
M11
N11
L10
M10
N10
K9
(1)
IO_L02N_4/D0/DIN
IO_L02P_4/D1
IO_L03N_4/D2/ALT_VRP_4
IO_L03P_4/D3/ALT_VRN_4
IO_L94N_4/VREF_4
IO_L94P_4
N9
K8
IO_L95N_4/GCLK3S
IO_L95P_4/GCLK2P
IO_L96N_4/GCLK1S
IO_L96P_4/GCLK0P
L8
M8
N8
K7
5
5
5
5
5
5
5
5
5
5
5
5
IO_L96N_5/GCLK7S
IO_L96P_5/GCLK6P
IO_L95N_5/GCLK5S
IO_L95P_5/GCLK4P
IO_L94N_5
N7
M7
N6
M6
L6
IO_L94P_5/VREF_5
IO_L03N_5/D4/ALT_VRP_5
IO_L03P_5/D5/ALT_VRN_5
IO_L02N_5/D6
K6
L5
K5
N4
M4
L4
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
K4
DS031-4 (v3.5) November 5, 2007
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Module 4 of 4
Product Specification
6
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