R
Virtex-II Platform FPGAs: Pinout Information
FG256/FGG256 Fine-Pitch BGA Package
As shown in Table 6, XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the
FG256/FGG256 fine-pitch BGA package. The pins in the XC2V250, XC2V500, and XC2V1000 devices are same. The No
Connect columns show pin differences for the XC2V40 and XC2V80 devices. Following this table are the FG256/FGG256
Fine-Pitch BGA Package Specifications (1.00mm pitch).
Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
0
Pin Description
IO_L01N_0
Pin Number
C4
No Connect in XC2V40 No Connect in XC2V80
0
IO_L01P_0
B4
0
IO_L02N_0
D5
0
IO_L02P_0
C5
0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L04N_0/VREF_0
IO_L04P_0
B5
0
A5
0
D6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0
C6
0
IO_L05N_0
B6
0
IO_L05P_0
A6
0
IO_L92N_0
E6
0
IO_L92P_0
E7
0
IO_L93N_0
D7
0
IO_L93P_0
C7
0
IO_L94N_0/VREF_0
IO_L94P_0
B7
0
A7
0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
D8
0
C8
0
B8
0
A8
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
A9
B9
C9
D9
A10
B10
C10
D10
E10
IO_L94P_1/VREF_1
IO_L93N_1
NC
NC
NC
NC
NC
NC
IO_L93P_1
IO_L92N_1
DS031-4 (v3.5) November 5, 2007
Product Specification
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