R
Virtex-II Platform FPGAs: Pinout Information
CS144/CSG144 Chip-Scale BGA
Package
As shown in Table 5, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144/CSG144 package. Pins
in the XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 device, shown in the
No Connect column. Following this table are the CS144/CSG144 Chip-Scale BGA Package Specifications (0.80mm pitch).
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
IO_L01N_0
Pin Number
No Connect in the XC2V40
0
0
0
0
0
0
0
0
0
0
0
0
B3
A3
C4
B4
A4
D5
A5
D6
C6
B6
A6
D7
IO_L01P_0
IO_L02N_0
IO_L02P_0
IO_L03N_0/VRP_0
IO_L03P_0/VRN_0
IO_L94N_0/VREF_0
IO_L94P_0
IO_L95N_0/GCLK7P
IO_L95P_0/GCLK6S
IO_L96N_0/GCLK5P
IO_L96P_0/GCLK4S
1
1
1
1
1
1
1
1
1
1
1
1
IO_L96N_1/GCLK3P
IO_L96P_1/GCLK2S
IO_L95N_1/GCLK1P
IO_L95P_1/GCLK0S
IO_L94N_1
A7
B7
A8
B8
C8
IO_L94P_1/VREF_1
IO_L03N_1/VRP_1
IO_L03P_1/VRN_1
IO_L02N_1
D8
C9
D9
A10
B10
C10
D10
IO_L02P_1
IO_L01N_1
IO_L01P_1
2
2
2
2
2
2
2
2
2
2
IO_L01N_2
IO_L01P_2
C13
D11
D12
D13
E10
E11
E13
F11
F12
G10
IO_L02N_2/VRP_2
IO_L02P_2/VRN_2
IO_L03N_2
IO_L03P_2/VREF_2
IO_L93N_2
NC
NC
IO_L93P_2/VREF_2
IO_L94N_2
IO_L94P_2
DS031-4 (v3.5) November 5, 2007
www.xilinx.com
Module 4 of 4
Product Specification
5
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