R
Virtex-II Platform FPGAs: Pinout Information
Description
Table 4: Virtex-II Pin Definitions (Continued)
Pin Name
PROG_B
Direction
Input
Active Low asynchronous reset to configuration logic. This pin has a permanent weak
pull-up resistor.
DONE
Input/Output DONE is a bidirectional signal with an optional internal pull-up resistor. As an output,
this pin indicates completion of the configuration process. As an input, a Low level on
DONE can be configured to delay the start-up sequence.
M2, M1, M0
HSWAP_EN
TCK
Input
Input
Input
Input
Output
Input
Configuration mode selection.
Enable I/O pull-ups during configuration.
Boundary Scan Clock.
TDI
Boundary Scan Data Input.
TDO
Boundary Scan Data Output.
TMS
Boundary Scan Mode Select.
PWRDWN_B
Input
Active Low power-down pin (unsupported). Driving this pin Low can adversely affect
(unsupported) device operation and configuration. PWRDWN_B is internally pulled High, which is its
default state. It does not require an external pull-up.
Other Pins
DXN, DXP
N/A
Temperature-sensing diode pins (Anode: DXP, Cathode: DXN).
V
Input
Decryptor key memory backup supply. Connect V
not used.
to V or GND if battery is
CCAUX
BATT
BATT
RSVD
N/A
Reserved pin - do not connect.
V
V
V
Input
Input
Input
Input
Power-supply pins for the output drivers (per bank).
Power-supply pins for auxiliary circuits.
Power-supply pins for the internal core logic.
Ground.
CCO
CCAUX
CCINT
GND
Notes:
1. All dedicated pins (JTAG and configuration) are powered by VCCAUX (independent of the bank VCCO voltage).
DS031-4 (v3.5) November 5, 2007
Product Specification
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