R
Virtex-II Platform FPGAs: Pinout Information
Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
Pin Number
No Connect in the XC2V40
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
M13
B1
N12
N2
M1
M2
M2
M3
TCK
B12
C1
TDI
TDO
C11
A13
M12
A1
TMS
PWRDWN_B
HSWAP_EN
RSVD
RSVD
VBATT
RSVD
A2
B2
A12
B11
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
GND
C2
N1
N13
B13
H2
L7
H13
C7
E1
GND
G2
J1
GND
GND
J4
GND
M5
L9
GND
GND
J11
H10
F13
E12
B9
GND
GND
GND
GND
GND
C5
1. See Table 4 for an explanation of the signals available on this pin.
DS031-4 (v3.5) November 5, 2007
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Product Specification
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