R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Revision
Date
Version
03/01/05
(cont’d)
3.4
(cont’d)
•
•
Table 15, Table 17, Table 18, and Table 19: Restructured these I/O-related tables to
include descriptions, as well as the actual IOSTANDARD attributes (used in Xilinx
ISE™ software) for all I/O standards.
Table 15: Added data for the following I/O standards: SSTL18_I, SSTL18_II,
SSTL18_I_DCI, SSTL18_II_DCI, HSTL_I_18, HSTL_II_18, HSTL_III_18,
HSTL_IV_18, LVDSEXT_25, LVDSEXT_33, BLVDS_25, LVDS_25_DCI,
LVDS_33_DCI, LVDSEXT_25_DCI, LVDSEXT_33_DCI, HSLVDCI_15, HSLVDCI_18,
HSLVDCI_25, HSLVDCI_33. Rearranged I/O standards in a more logical order.
•
•
Table 16: Added parameter T
Table 17: Added data for the following I/O standards: SSTL18_I, SSTL18_II,
SSTL18_I_DCI, SSTL18_II_DCI, HSLVDCI_15, HSLVDCI_18, HSLVDCI_25,
(Minimum Pulse Width, SR Input).
RPW
HSLVDCI_33. Changed “Csl” to “C
” to agree with Figure 1 and Table 19.
REF
Rearranged I/O standards in a more logical order.
•
•
Table 18: Added data for the following I/O standards: SSTL18_I, SSTL18_II,
HSTL_I_18, HSTL_II_18, HSTL_III_18, HSTL_IV_18. Added footnote defining
equivalents for DCI standards.
Table 19: Added Footnotes (2) and (3) to PCI/PCI-X capacitive load (C
Added HSLVDCI callouts to LVDCI parameter rows (same values).
) values.
REF
•
•
Table 28: Added parameter T
Table 31: Added Footnote (1) indicating that F
, CLKA to CLKB Setup Time.
BCCS
should not exceed
CC_SERIAL
F
if no provision is made to adjust the speed of CCLK.
CC_STARTUP
•
•
Table 33: T
corrected from a “Min” to a “Max” specification.
TCKTDO
11/05/07
3.5
Updated copyright notice and legal disclaimer.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
•
Virtex-II Platform FPGAs: Introduction and Overview
(Module 1)
Virtex-II Platform FPGAs: Functional Description
(Module 2)
•
•
Virtex-II Platform FPGAs: DC and Switching
Characteristics (Module 3)
Virtex-II Platform FPGAs: Pinout Information
(Module 4)
•
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
44
XILINX [ XILINX, INC ]
