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DS031 参数 Datasheet PDF下载

DS031图片预览
型号: DS031
PDF下载: 下载PDF文件 查看货源
内容描述: 的Virtex -II FPGA平台:完整的数据表 [Virtex-II Platform FPGAs: Complete Data Sheet]
分类和应用:
文件页数/大小: 318 页 / 2407 K
品牌: XILINX [ XILINX, INC ]
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R
Virtex-II Platform FPGAs: DC and Switching Characteristics  
Speed Grade  
Table 47: Sample Window  
Description  
Sampling Error at Receiver Pins(1)  
Symbol  
Device  
XC2V40  
-6  
-5  
-4  
Units  
ps  
TSAMP  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
500  
550  
550  
550  
550  
550  
550  
550  
550  
550  
550  
550  
XC2V80  
ps  
XC2V250  
XC2V500  
XC2V1000  
XC2V1500  
XC2V2000  
XC2V3000  
XC2V4000  
XC2V6000  
XC2V8000  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
Notes:  
1. This parameter indicates the total sampling error of Virtex-II DDR input registers across voltage, temperature, and process. The  
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:  
- CLK0 and CLK180 DCM jitter  
- Worst-case Duty-Cycle Distortion - TDCD_CLK180  
- DCM accuracy (phase offset)  
- DCM phase shift resolution.  
These measurements do not include package or clock tree skew.  
Table 48: Pin-to-Pin Setup/Hold: Source-Synchronous Configuration  
Speed Grade  
Description  
Symbol  
Device  
-6  
-5  
-4  
Units  
Data Input Set-Up and Hold Times Relative to a Forwarded  
Clock Input Pin, Using DCM and Global Clock Buffer.  
For situations where clock and data inputs conform to  
different standards, adjust the setup and hold values  
accordingly using the values shown in IOB Input Switching  
Characteristics Standard Adjustments, page 11.  
No Delay  
TPSDCM  
TPHDCM  
/
XC2V40  
XC2V80  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.6  
0.2/0.6  
0.2/0.6  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.5  
0.2/0.6  
0.2/0.6  
0.2/0.6  
0.2/0.7  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Global Clock and IFF with DCM  
XC2V250  
XC2V500  
XC2V1000  
XC2V1500  
XC2V2000  
XC2V3000  
XC2V4000  
XC2V6000  
XC2V8000  
Notes:  
1. IFF = Input Flip-Flop  
2. The timing values were measured using the fine-phase adjustment feature of the DCM.  
3. The worst-case duty-cycle distortion and DCM jitter on CLK0 and CLK180 is included in these measurements.  
DS031-3 (v3.5) November 5, 2007  
Product Specification  
www.xilinx.com  
Module 3 of 4  
40  
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