R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Revision
Date
Version
08/01/03
3.0
•
•
Table 13: All Virtex-II devices and speed grades now Production.
Updated values in Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables, based on values extracted from speedsfile version 1.116.
Table 34 and Table 35: Revised test setup footnote to refer to Figure 1. Previously
specified a capacitive load parameter.
•
•
•
Figure 1: Added note to figure regarding termination resistors.
10/14/03
3.1
Table 1: Changed T description from “Operating junction temperature” to “Maximum
J
junction temperature”.
•
•
In section General Power Supply Requirements, replaced reference to Answer Record
11713 with reference to XAPP689 regarding handling of simultaneously switching
outputs (SSO).
In section I/O Standard Adjustment Measurement Methodology:
-
-
-
-
Table 18 renamed Input Delay Measurement Methodology. Added footnotes.
Added new Table 19, Output Delay Measurement Methodology.
Replaced Figure 1, Generalized Test Setup, with new drawing.
Revised and extended text describing output delay measurement procedure.
•
•
Table 45, Table 47, and Table 48: All Source-Synchronous parameters for all devices
now available in these tables.
XC2V8000 is no longer offered in the -6 speed grade. The following tables containing
parameters or other references to this device/grade combination were corrected
accordingly: Table 13, Table 14, Table 34, Table 35, Table 36, Table 37, Table 45,
Table 47, and Table 48.
•
•
Table 39: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing
Footnote (2) to new Footnote (3).
03/29/04
3.2
Table 4:
-
-
For XC2V40, added Maximum quiescent supply current specifications.
For all devices, updated Typical specifications for I and I
.
CCAUXQ
CCINTQ
•
•
Section Power-On Power Supply Requirements, page 3: Added Footnote (1) qualifying
statement that power supplies can be turned on in any sequence.
Added section Configuration Timing, page 27. This section includes new timing
diagrams as well as parameter specification tables formerly included in the Virtex-II
Platform FPGA User Guide.
•
•
Table 20, Clock Distribution Switching Characteristics: Added parameter T /T
GSI GIS
(Global Clock Buffer S Input Setup/Hold to I1 and I2 Inputs).
Table 38, Operating Frequency Ranges: Added Footnote (4) to all four CLKIN
parameters.
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•
•
Recompiled for backward compatibility with Acrobat 4 and above.
06/24/04
03/01/05
3.3
3.4
Table 1: Added T
parameters for Pb-free package devices.
SOL
Updated values in Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables, based on values extracted from speedsfile version 1.120.
•
Table 2: Corrected Footnote (1) to require connecting V
battery is not used.
to V
or GND if
BATT
CCAUX
•
•
Table 3: Corrected "V
current per bank" to "V
current per pin."
REF
REF
Section Power-On Power Supply Requirements: Added word “monotonically” to
description of supply voltage ramp-on requirements. Added sentence to footnote (1)
indicating that if the stated requirements are violated, no damage to the device will
result, but configuration will probably fail.
•
Figure 3 and Figure 4: Corrected to show DOUT transitions driven by falling edge of
CCLK.
DS031-3 (v3.5) November 5, 2007
Product Specification
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