R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Source Synchronous Timing Budgets
This section describes how to use the parameters provided in the Source-Synchronous Switching Characteristics section to
develop system-specific timing budgets. The following analysis provides information necessary for determining Virtex-II
contributions to an overall system timing analysis; no assumptions are made about the effects of Inter-Symbol Interference
or PCB skew.
Virtex-II Transmitter Data-Valid Window (TX)
Virtex-II Receiver Data-Valid Window (RX)
T
is the minimum aggregate valid data period for a
R is the required minimum aggregate valid data period for
X
X
source-synchronous data bus at the pins of the device and
is calculated as follows:
a source-synchronous data bus at the pins of the device
and is calculated as follows:
(1)
(2)
(1)
(2)
(3)
T = Data Period - [Jitter + Duty Cycle Distortion
+
R = [TSAMP + TCKSKEW + TPKGSKEW
]
X
X
(3)
(4)
TCKSKEW + TPKGSKEW
]
Notes:
Notes:
1. This parameter indicates the total sampling error of Virtex-II
DDR input registers across voltage, temperature, and process.
The characterization methodology uses the DCM to capture
the DDR input registers’ edges of operation. These
measurements include:
1. Jitter values and accumulation methodology to be provided in
a future release of this document. The absolute period jitter
values found in the DCM Timing Parameters section of the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
-
-
-
-
CLK0 and CLK180 DCM jitter in a quiet system
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
2. This value depends on the clocking methodology used. See
Note1 for Table 45.
3. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
4. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
DCM phase shift resolution.
These measurements do not include package or clock tree
skew.
2. This value represents the worst-case clock-tree skew
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
3. These values represent the worst-case skew between any two
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
Revision History
This section records the change history for this module of the data sheet.
Date
Version
1.0
Revision
11/07/00
12/06/00
01/15/01
Early access draft.
Initial release.
1.1
1.2
Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II
Switching Characteristics sections.
01/25/01
1.3
1.5
•
•
The data sheet was divided into four modules (per the current style standard).
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•
•
Table 18, “Delay Measurement Methodology”
04/23/01
Updated values in the Virtex-II Performance Characteristics and Virtex-II Switching
Characteristics tables.
•
•
Added T
symbol to Table 23.
REG32
Skipped v1.4 to sync with other modules. Reverted to traditional double-column format.
DS031-3 (v3.5) November 5, 2007
Product Specification
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