R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Output Clock Jitter
Table 40: Output Clock Jitter
Speed Grade
Description
Clock Synthesis Period Jitter
CLK0
Symbol
Constraints
-6
-5
-4
Units
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
CLKOUT_PER_JITT_FX
100
150
150
150
200
150
300
100
150
150
150
200
150
300
100
150
150
150
200
150
300
ps
ps
ps
ps
ps
ps
ps
ps
CLK90
CLK180
CLK270
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
Notes:
Note 1 Note 1 Note 1
1. Values for this parameter are available at www.xilinx.com.
Output Clock Phase Alignment
Table 41: Output Clock Phase Alignment
Speed Grade
Description
Symbol
Constraints
-6
-5
-4
Units
ps
Phase Offset Between CLKIN and CLKFB
CLKIN/CLKFB
CLKIN_CLKFB_PHASE
50
50
50
Phase Offset Between Any DCM Outputs
All CLK outputs
Duty Cycle Precision
DLL outputs(1)
CLKFX outputs
Notes:
CLKOUT_PHASE
140
140
140
ps
CLKOUT_DUTY_CYCLE_DLL(2)
CLKOUT_DUTY_CYCLE_FX
150
100
150
100
150
100
ps
ps
1. "DLL outputs" is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE.
3. Specification also applies to PSCLK.
DS031-3 (v3.5) November 5, 2007
Product Specification
www.xilinx.com
Module 3 of 4
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