R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Input Clock Tolerances
Table 39: Input Clock Tolerances
Speed Grade
-6
-5
-4
Constraints
FCLKIN
Description
Symbol
Min
Max
Min
Max
Min
Max
Units
Input Clock Low/High Pulse Width
PSCLK
PSCLK_PULSE
< 1MHz
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
25.00
25.00
10.00
5.00
3.00
2.40
2.00
1.80
1.50
1.30
1.15
1.05
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 – 10 MHz
10 – 25 MHz
25 – 50 MHz
50 – 100 MHz
100 – 150 MHz
150 – 200 MHz
200 – 250 MHz
250 – 300 MHz
300 – 350 MHz
350 – 400 MHz
> 400 MHz
PSCLK_PULSE and
CLKIN_PULSE
PSCLK and CLKIN(3)
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_FX_LF
300
300
300
300
300
300
ps
ps
CLKIN (using CLKFX outputs)(2)
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_CYC_JITT_DLL_HF
CLKIN_CYC_JITT_FX_HF
150
150
150
150
150
150
ps
ps
CLKIN (using CLKFX outputs)(2)
Input Clock Period Jitter (Low Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_PER_JITT_DLL_LF
CLKIN_PER_JITT_FX_LF
1
1
1
1
1
1
ns
ns
CLKIN (using CLKFX outputs)(2)
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN_PER_JITT_DLL_HF
CLKIN_PER_JITT_FX_HF
1
1
1
1
1
1
ns
ns
CLKIN (using CLKFX outputs)(2)
Feedback Clock Path Delay Variation
CLKFB off-chip feedback
CLKFB_DELAY_VAR_EXT
1
1
1
ns
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If DCM phase shift feature is used and CLKIN frequency > 200 Mhz, CLKIN duty cycle must be within 5% (45/55 to 55/45).
DS031-3 (v3.5) November 5, 2007
Product Specification
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