R
Virtex-II Platform FPGAs: Pinout Information
Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number
No Connect in XC2V40 No Connect in XC2V80
5
IO_L01P_5/CS_B
T3
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L01P_6
IO_L01N_6
P1
N1
N3
N2
M4
M3
M2
M1
L4
L3
L2
L1
L5
K5
K4
K3
K2
K1
J4
IO_L02P_6/VRN_6
IO_L02N_6/VRP_6
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
NC
NC
NC
NC
IO_L04N_6
IO_L06P_6
IO_L06N_6
IO_L43P_6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L43N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L91P_6
IO_L91N_6
IO_L93P_6
IO_L93N_6/VREF_6
IO_L94P_6
IO_L94N_6
J3
IO_L96P_6
J2
IO_L96N_6
J1
7
7
7
7
7
7
7
7
7
IO_L96P_7
IO_L96N_7
H1
H2
H3
H4
G1
G2
G3
G4
G5
IO_L94P_7
IO_L94N_7
IO_L93P_7/VREF_7
IO_L93N_7
NC
NC
NC
NC
NC
IO_L91P_7
IO_L91N_7
IO_L45P_7/VREF_7
NC
DS031-4 (v3.5) November 5, 2007
Product Specification
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