R
Virtex-II Platform FPGAs: Pinout Information
Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
IO_L45N_7
Pin Number
No Connect in XC2V40 No Connect in XC2V80
7
7
7
7
7
7
7
7
7
7
7
7
7
F5
F1
F2
F3
F4
E1
E2
E3
E4
D2
D3
D1
C1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO_L43P_7
IO_L43N_7
IO_L06P_7
IO_L06N_7
IO_L04P_7
IO_L04N_7
IO_L03P_7/VREF_7
IO_L03N_7
IO_L02P_7/VRN_7
IO_L02N_7/VRP_7
IO_L01P_7
IO_L01N_7
0
0
0
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
VCCO_0
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
VCCO_3
VCCO_3
VCCO_3
VCCO_4
VCCO_4
VCCO_4
VCCO_5
VCCO_5
VCCO_5
VCCO_6
VCCO_6
F8
F7
E8
F10
F9
E9
H12
H11
G11
K11
J12
J11
M9
L10
L9
M8
L8
L7
K6
J6
DS031-4 (v3.5) November 5, 2007
Product Specification
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