R
Virtex-II Platform FPGAs: Pinout Information
Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
Pin Number
No Connect in XC2V40 No Connect in XC2V80
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Notes:
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
T16
T1
R15
R2
P14
P3
L11
L6
K10
K9
K8
K7
J10
J9
J8
J7
H10
H9
H8
H7
G10
G9
G8
G7
F11
F6
C14
C3
B15
B2
A16
A1
1. See Table 4 for an explanation of the signals available on this pin.
DS031-4 (v3.5) November 5, 2007
Product Specification
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