R
Virtex-II Platform FPGAs: Pinout Information
Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000
Bank
Pin Description
VCCO_6
Pin Number
No Connect in XC2V40 No Connect in XC2V80
6
7
7
7
J5
H6
H5
G6
VCCO_7
VCCO_7
VCCO_7
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CCLK
PROG_B
DONE
M0
P15
A2
R14
T2
M1
P2
M2
R3
HSWAP_EN
TCK
B3
A15
C2
TDI
TDO
C15
B14
T15
A4
TMS
PWRDWN_B
RSVD
RSVD
VBATT
RSVD
A3
A14
A13
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
R16
R1
B16
B1
N13
N4
M12
M5
E12
E5
D13
D4
DS031-4 (v3.5) November 5, 2007
Product Specification
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