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X4045S8I-4.5A 参数 Datasheet PDF下载

X4045S8I-4.5A图片预览
型号: X4045S8I-4.5A
PDF下载: 下载PDF文件 查看货源
内容描述: CPU监控与4k位EEPROM [CPU Supervisor with 4Kbit EEPROM]
分类和应用: 电源电路电源管理电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 25 页 / 137 K
品牌: XICOR [ XICOR INC. ]
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X4043/45  
Figure 10. Byte Write Sequence  
.
S
t
a
r
S
t
o
p
Signals from  
the Master  
Byte  
Address  
Slave  
Address  
Data  
t
SDA Bus  
0
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Page Write  
goes back to ‘0’ on the same page. This means that the  
master can write 16 bytes to the page starting at any  
location on that page. If the master begins writing at  
location 10, and loads 12 bytes, then the first 5 bytes  
are written to locations 10 through 15, and the last 7  
bytes are written to locations 0 through 6. Afterwards,  
the address counter would point to location 7 of the  
page that was just written. If the master supplies more  
than 16 bytes of data, then new data over-writes the  
previous data, one byte at a time.  
The device is capable of a page write operation. It is  
initiated in the same manner as the byte write opera-  
tion; but instead of terminating the write cycle after the  
first data byte is transferred, the master can transmit  
an unlimited number of 8-bit bytes. After the receipt of  
each byte, the device will respond with an acknowl-  
edge, and the address is internally incremented by  
one. The page address remains constant. When the  
counter reaches the end of the page, it “rolls over” and  
Figure 11. Page Write Operation  
(1 n 16)  
S
t
a
r
S
t
o
p
Signals from  
the Master  
Data  
(1)  
Data  
(n)  
Slave  
Address  
Byte  
Address  
t
SDA Bus  
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from  
the Slave  
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10  
5 Bytes  
7 Bytes  
Address Pointer  
Ends Here  
Addr = 7  
Address  
Address  
= 6  
Address  
n-1  
10  
The master terminates the data byte loading by issuing  
a stop condition, which causes the device to begin the  
nonvolatile write cycle. As with the byte write operation,  
all inputs are disabled until completion of the internal  
write cycle. See Figure 11 for the address, acknowl-  
edge, and data transfer sequence.  
Stops and Write Modes  
Stop conditions (that terminate write operations) must  
be sent by the master after sending at least 1 full data  
byte, plus the subsequent ACK signal. If a stop is  
issued in the middle of a data byte, or before 1 full data  
byte plus its associated ACK is sent, then the device  
will reset itself without performing the write. The con-  
tents of the array will not be effected.  
Characteristics subject to change without notice. 10 of 25  
REV 1.1.17 9/14/01  
www.xicor.com  
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