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X4045S8I-4.5A 参数 Datasheet PDF下载

X4045S8I-4.5A图片预览
型号: X4045S8I-4.5A
PDF下载: 下载PDF文件 查看货源
内容描述: CPU监控与4k位EEPROM [CPU Supervisor with 4Kbit EEPROM]
分类和应用: 电源电路电源管理电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 25 页 / 137 K
品牌: XICOR [ XICOR INC. ]
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X4043/45  
SERIAL INTERFACE  
transfers, and provides the clock for both transmit and  
receive operations. Therefore, the devices in this family  
operate as slaves in all applications.  
Serial Interface Conventions  
The device supports a bidirectional bus oriented proto-  
col. The protocol defines any device that sends data  
onto the bus as a transmitter, and the receiving device  
as the receiver. The device controlling the transfer is  
called the master and the device being controlled is  
called the slave. The master always initiates data  
Serial Clock and Data  
Data states on the SDA line can change only during  
SCL LOW. SDA state changes during SCL HIGH are  
reserved for indicating start and stop conditions. See  
Figure 6.  
Figure 6. Valid Data Changes on the SDA Bus  
SCL  
SDA  
Data Stable  
Data Change  
Data Stable  
Serial Start Condition  
Serial Stop Condition  
All commands are preceded by the start condition,  
which is a HIGH to LOW transition of SDA when SCL is  
HIGH. The device continuously monitors the SDA and  
SCL lines for the start condition and will not respond to  
any command until this condition has been met. See  
Figure 7.  
All communications must be terminated by a stop condi-  
tion, which is a LOW to HIGH transition of SDA when  
SCL is HIGH. The stop condition is also used to place  
the device into the standby power mode after a read  
sequence. A stop condition can only be issued after the  
transmitting device has released the bus. See Figure 6.  
Figure 7. Valid Start and Stop Conditions  
SCL  
SDA  
Start  
Stop  
Serial Acknowledge  
address byte. If a write operation is selected, the  
device will respond with an acknowledge after the  
receipt of each subsequent eight bit word. The device  
will acknowledge all incoming data and address bytes,  
except for the slave address byte when the device  
identifier and/or select bits are incorrect.  
Acknowledge is a software convention used to indicate  
successful data transfer. The transmitting device, either  
master or slave, will release the bus after transmitting  
eight bits. During the ninth clock cycle, the receiver will  
pull the SDA line LOW to acknowledge that it received  
the eight bits of data. Refer to Figure 8.  
In the read mode, the device will transmit eight bits of  
data, release the SDA line, then monitor the line for an  
acknowledge. If an acknowledge is detected and no  
The device will respond with an acknowledge after rec-  
ognition of a start condition and if the correct device  
identifier and select bits are contained in the slave  
Characteristics subject to change without notice. 8 of 25  
REV 1.1.17 9/14/01  
www.xicor.com  
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