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WM8983
REGISTER
ADDRESS
BIT
LABEL
PLLPRESCALE
PLLN
DEFAULT
DESCRIPTION
R36
4
0
Divide MCLK by 2 before input to
PLL
PLL N value
3:0
5:0
1000
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R37
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
0Ch
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
PLL K value
1
R38
8:0
8:0
093h
0E9h
PLL K Value
2
R39
PLL K Value
3
Table 53 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 54.
MCLK
(MHz)
(F1)
12
DESIRED
OUTPUT
(MHz)
F2
PRESCALE
DIVIDE
MCLKDIV
R
PLLN
K
PLLK
PLLK
[17:9]
R38 (Hex)
161
93
PLLK
[8:0]
R39 (Hex)
26
(MHz)
R36
(Hex)
[23:18]
(Hex)
7
R37 (Hex)
11.29
12.288
11.29
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
7.5264
8.192
86C226
3126E8
F28BD4
8FD525
45A1CA
D3A06E
6872AF
3D70A3
2DB492
FD809F
1F76F7
EE009E
86C226
3126E8
F28BD4
8FD525
BOAC93
482296
21
C
12
8
E9
13
6.947446
7.561846
6.272
6
3C
23
11
34
1A
F
145
1EA
D0
1D4
126
1CA
6D
13
12.288
11.29
7
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
6
12.288
11.29
6.826667
9.408
6
1D0
39
9
B0
12.288
11.29
10.24
A
9
B8
A3
9.178537
9.990243
9.122909
9.929697
7.5264
B
DA
92
12.288
11.29
9
3F
7
C0
9F
9
1BB
100
161
93
F8
12.288
11.29
9
3B
21
C
9E
7
26
24
12.288
11.29
8.192
8
E9
26
6.947446
7.561846
6.690133
7.281778
6
3C
23
2C
12
145
1EA
56
1D4
126
94
26
12.288
11.29
7
27
6
27
12.288
7
11
96
Table 54 PLL Frequency Examples for Common MCLK Rates
PP Rev 1.1 August 2005
71
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
