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WM8983GEFLR 参数 Datasheet PDF下载

WM8983GEFLR图片预览
型号: WM8983GEFLR
PDF下载: 下载PDF文件 查看货源
内容描述: 移动多媒体编解码器1W扬声器驱动器 [Mobile Multimedia CODEC with 1W Speaker Driver]
分类和应用: 解码器驱动器编解码器
文件页数/大小: 88 页 / 1508 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Product Preview  
WM8983  
LOOPBACK  
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data  
from the ADC audio interface is fed directly into the DAC data input.  
COMPANDING  
The WM8983 supports A-law and µ-law companding on both transmit (ADC) and receive (DAC)  
sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate  
value to the DAC_COMP or ADC_COMP register bits respectively.  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADC companding  
R5  
2:1  
ADC_COMP  
0
Companding  
Control  
00 = off  
01 = reserved  
10 = µ-law  
11 = A-law  
4:3  
DAC_COMP  
0
0
DAC companding  
00 = off  
01 = reserved  
10 = µ-law  
11 = A-law  
5
WL8  
0 = off  
1 = device operates in 8-bit mode.  
Table 49 Companding Control  
Companding involves using a piecewise linear approximation of the following equations (as set out  
by ITU-T G.711 standard) for data compression:  
µ-law (where µ=255 for the U.S. and Japan):  
F(x) = ln( 1 + µ|x|) / ln( 1 + µ)  
law (where A=87.6 for Europe):  
F(x) = A|x| / ( 1 + lnA)  
-1  
x
1
} for x 1/A  
} for 1/A 1  
F(x) = ( 1 + lnA|x|) / (1 + lnA)  
x
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted  
for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s  
of data.  
Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The  
input data range is separated into 8 levels, allowing low amplitude signals better precision than that  
of high amplitude signals. This is to exploit the operation of the human auditory system, where  
louder sounds do not require as much resolution as quieter sounds. The companded signal is an 8-  
bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).  
Setting the WL8 register bit allows the device to operate with 8-bit data. In this mode it is possible to  
use 8 BCLK’s per LRC frame. When using DSP mode B, this allows 8-bit data words to be output  
consecutively every 8 BCLK’s and can be used with 8-bit data words using the A-law and u-law  
companding functions.  
BIT8  
BIT[7:4]  
BIT[3:0]  
SIGN  
EXPONENT  
MANTISSA  
Table 50 8-bit Companded Word Composition  
PP Rev 1.1 August 2005  
67  
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