WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC digital volume update
R11 (0Bh)
Right DAC
volume
8
DACVU
0
Writing 1 to this bit will cause left and right
DAC volumes to be updated (LDACVOL and
RDACVOL)
Right DAC digital volume
FFh -> C0h : 0dB
BFh : -0.375dB
7:0
RDACVOL[7:0] 1111_1111
Beh: -0.75dB
….. in steps of -0.375dB to
02h: -71.25dB
01h: -71.625dB
00h: Digital Mute
Register 0Bh Right DAC volume
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Integer divide of BCLK. 50:50 LRCLK duty cycle is only guaranteed
R14 (0Eh)
Audio
8:0
LRCLK_RATE[8:0] 0_0100_0000
with even values (4, 6, … … , 510).
0_0000_0000 to 0_0000_0011 : reserved
0_0000_0100 : 4
Interface 2
…
0_0100_0000 : 64
…
1_1111_1110 : 510
1_1111_1111: Reserved
Register 0Eh Audio Interface 2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R15 (0Fh)
Software
Reset
15:0 SW_RST_DEV_ID1[15:0] 0001_1000_0000_0001 Software Reset
Register 0Fh Software Reset
PP, August 2009, Rev 3.1
w
88
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
