WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Write 1 to do volume update on outputs
R2 (02h)
LOUT1
volume
8
7
OUT1VU
LO1ZC
0
0
Left HP output zero cross enable
Left HP output PGA gain, 1dB steps
6:0
LOUT1VOL[6:0] 000_0000
0000000 to 0101111 : Mute
0110000 : -73dB
…
1111001 : 0dB
…
1111111 : +6dB
Register 02h LOUT1 volume
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R3 (03h)
ROUT1
volume
8
7
OUT1VU
RO1ZC
0
0
Write 1 to do volume update on outputs
Right HP output zero cross enable
Right HP output PGA gain, 1dB steps
6:0
ROUT1VOL[6:0] 000_0000
0000000 to 0101111 : Mute
0110000 : -73dB
…
1111001 : 0dB
…
1111111 : +6dB
Register 03h ROUT1 volume
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Defines the ADC 256fs clock, which is further divided by 2.
R4 (04h)
8:6
ADCDIV[2:0]
000
Clocking1
000 : 256fs = SYSCLK / 1.0 (default =12.288MHz, fs= 48 KHz)
001 : Reserved
010 : 256fs = SYSCLK / 2
011 : 256fs = SYSCLK / 3
100 : 256fs = SYSCLK / 4
101 : 256fs = SYSCLK / 5.5
110 : 256fs = SYSCLK / 6
111 : Reserved
Defines the DAC clock.
5:3
DACDIV[2:0]
100
000 : DAC clock = SYSCLK / 1
001 : Reserved
010 : DAC clock = SYSCLK / 2
011 : DAC clock = SYSCLK / 3
100 : DAC clock = SYSCLK / 4 (default =3.072 MHz when
SYSCLK=12.288MHz)
101 : DAC clock = SYSCLK / 5.5
110 : DAC clock = SYSCLK / 6
111 : Reserved
Pre-divide MCLK to get SYSCLK.
0 : Divide by 1
2
MCLKDIV
0
1 : Divide by 2
Register 04h Clocking1
PP, August 2009, Rev 3.1
w
84
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
