WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Swaps L and R ADC data in interface
R7 (07h)
Audio
Interface 0
8
7
ALRSWAP
BCLKINV
0
0
BCLK invert bit (for master and slave modes)
0 : BCLK not inverted
1 : BCLK inverted
Master / Slave Mode Control
0 : Enable slave mode
6
MS
0
1 : Enable master mode
Swap Left/Right channels on DAC path
5
4
DLRSWAP
LRP
0
0
Right, Left and I2S modes – LRC polarity
0 : normal LRC polarity
1 : invert LRC polarity
DSP Mode – mode A/B select
0 : MSB is available on 2nd BCLK rising edge
after LRC rising edge (mode A)
1 : MSB is available on 1st BCLK rising edge
after LRC rising edge (mode B)
Audio Interface Word Length
00 : 16 bit
01 : 20 bit
10 : 24 bit
11 : 32 bit
Audio Interface Format
00: Right Justified
3:2
1:0
WL[1:0]
10
10
FORMAT[1:0]
01: Left Justified
10: I2S
11: DSP
Register 07h Audio Interface 0
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
Clocking2
8:6
DCLKDIV[2:0]
111
Class D switching clock divider.
000 = SYSCLK / 1
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16 (default for 12.288MHz/16 = 768 KHz)
(Note that Class D function further divides by 2 to run at 384 KHz)
Enable system clock. Power saving feature to gate clock to digital.
When this bit is enabled, an MCLK must be provided to allow access to
the control interface.
5
CLK_SYS_ENA
1
DSP clock enable. Power saving feature to gate clock to DSP while
allowing auxiliary functions to run
4
CLK_DSP_ENA
BCLKDIV[3:0]
1
BCLK Frequency (Master Mode)
0000 = SYSCLK
3:0
0100
0001 = Reserved
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4 (default)
0101 = Reserved
0110 = SYSCLK / 6
0111 = SYSCLK / 8
PP, August 2009, Rev 3.1
w
86
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
