WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
00 = off
R25 (19h)
8:7
VMIDSEL[1:0]
00
01 = 2x50k
10 = 2x250k
11 = 2x5k
Pwr Mgmt (1)
Enable master bias current source
Enables Left PGA and boost mixer
Enables Right PGA and boost mixer
Enable ADC Left channel
6
5
4
3
2
1
VREF
AINL
0
0
0
0
0
0
AINR
ADCL
ADCR
MICB
Enable ADC Right channel
Enable MICBIAS circuit
Register 19h Pwr Mgmt (1)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Enable left DAC channel
Enable right DAC channel
Enable left headphone PGA
Enable right headphone PGA
Enable left speaker PGA
Enable right speaker PGA
R26 (1Ah)
Pwr Mgmt (2)
8
7
6
5
4
3
DACL
0
0
0
0
0
0
DACR
LOUT1_PGA
ROUT1_PGA
SPKL_PGA
SPKR_PGA
Register 1Ah Pwr Mgmt (2)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R27 (1Bh)
Additional
control (3)
2:0
SAMPLE_RATE[2:0]
000
Sample Rate Control for ALC and auto configuration
000 : 44.1k/48k
001 : 32k
010 : 22.05k/24k
011 : 16k
100 : 11.25k/12k
101 : 8k
110-111 : reserved
Register 1Bh Additional control (3)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Enables fast startup bias gen
R28 (1Ch)
Anti-pop
4
3
2
BUFDCOPEN
BUFIOEN
0
0
0
Enables fast startup bias and vmid buffers
Enables VMID soft start
0 : Disabled
SOFT_ST
1 : Enabled
Register 1Ch Anti-pop
PP, August 2009, Rev 3.1
w
92
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
