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WM8961 参数 Datasheet PDF下载

WM8961图片预览
型号: WM8961
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗立体声编解码器与1W立体声D类扬声器驱动器和接地参考耳机驱动器 [Ultra-Low Power Stereo CODEC with 1W Stereo Class D Speaker Drivers and Ground Referenced Headphone Drivers]
分类和应用: 解码器驱动器编解码器
文件页数/大小: 116 页 / 1413 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8961  
Pre-Production  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
ADC Data invert  
00 : Both Channels normal polarity  
01 : Left Channel Inverted  
R5 (05h)  
ADC and DAC  
Control 1  
6:5  
ADCPOL[1:0]  
00  
10 : Right Channel Inverted  
11 : Both Channels Inverted  
Digital DAC mute  
3
DACMU  
1
DAC De-emphasis Filter Control  
00: no de-emphasis  
2:1  
DEEMPH[1:0]  
00  
01: De-emphasis for 32kHz sample rate  
10: De-emphasis for 44.1kHz sample rate  
11: De-emphasis for 48kHz sample rate  
Disables high pass filter  
0
ADCHPD  
0
Register 05h ADC and DAC Control 1  
REGISTER  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
R6 (06h)  
ADC and DAC  
Control 2  
8:7  
ADC_HPF_CUT[1:0]  
00  
ADC High Pass Filter Cutoff  
00: Hi-fi mode (fc=4Hz at fs=48kHz)  
01: Voice mode 1 (fc=127 at fs=16kHz)  
10: Voice mode 2 (fc=130 at fs=8kHz)  
11: Voice mode 3 (fc=267Hz at fs=8kHz)  
(Note: fc scales with sample rate. See Table 14 for cut-off  
frequencies at all supported sample rates)  
DAC Data invert  
6:5  
DACPOL[1:0]  
00  
00 : Both Channels normal polarity  
01 : Left Channel Inverted  
10 : Right Channel Inverted  
11 : Both Channels Inverted  
0=No soft mute  
1=slow volume ramp when DAC muted/un-muted.  
3
2
DACSMM  
DACMR  
0
0
Select fast or slow volume ramp up and down  
0: Fast Ramp Rate (24kHz at fs=48k, providing maximum delay of  
10.7ms)  
1: Slow ramp rate (1.5kHz at fs=48kHz, providing maximum delay of  
171ms)  
Sloping stop band enable  
1
0
DACSLOPE  
0
0
DAC 128 Over Sampling Rate  
DAC_OSR128  
0: 64x DAC oversampling  
1: If MANUAL_MODE=0, automatically configure DACDIV[2:0] for  
128OSR mode. This will give a SNR improvement at the expense of  
power  
Register 06h ADC and DAC Control 2  
PP, August 2009, Rev 3.1  
w
85  
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