WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
1000 = Reserved
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 24
1100 = Reserved
1101 to 1111 = SYSCLK / 32
Register 08h Clocking2
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC data companding mode
00 : off
R9 (09h)
Audio
4:3
DACCOMP[1:0]
00
Interface 1
01 : reserved
10 : μ-law
11 : A-law
ADC data companding mode
00 : off
2:1
ADCCOMP[1:0]
LOOPBACK
00
0
01 : reserved
10 : μ-law
11 : A-law
Audio interface loopback mode enable
0 : No loopback
0
1 : Loopback enabled, ADC data output is fed directly into DAC data
input
Register 09h Audio Interface 1
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC digital volume update
R10 (0Ah)
Left DAC
volume
8
DACVU
0
Writing 1 to this bit will cause left and right
DAC volumes to be updated (LDACVOL and
RDACVOL)
7:0
LDACVOL[7:0] 1111_1111 Left DAC digital volume
FFh -> C0h : 0dB
BFh : -0.375dB
Beh: -0.75dB
….. in steps of -0.375dB to
02h: -71.25dB
01h: -71.625dB
00h: Digital Mute
Register 0Ah Left DAC volume
PP, August 2009, Rev 3.1
w
87
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
