WM8961
Pre-Production
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Determines the ALC mode of operation:
R19 (13h)
ALC3
8
ALCMODE
0
0 = ALC mode
1 = Limiter mode
ALCSEL[1:0] bits must be set to 00 before changing this bit.
ALC Decay (gain ramp-up) time
0000 : 24ms
0001 : 48ms
Doubling each step…
1010-1111 : 24.58s
7:4
3:0
DCY[3:0]
ATK[3:0]
0011
0010
ALC Attack (gain ramp-down) time
0000 : 6ms
0001 : 12ms
0010 : 24ms
… (time doubles with every step)
1010 to 1111 : 6.14s
Register 13h ALC3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Noise Gate Threshold
00000 : -76.5dB FS
00001 : -75dB FS
1.5dB steps…
R20 (14h)
Noise Gate
7:3
NGTH[4:0]
0_0000
1111-30dB FS
Noise gate mode
0 : Hold PGA gain static (recommended)
1 : Mute ADC output
1
0
NGG
0
0
Noise Gate Enable
NGAT
Register 14h Noise Gate
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
ADC digital volume update
Writing 1 to this bit will cause left and right ADC volumes to be updated
(LADCVOL and RADCVOL)
R21 (15h)
Left ADC
volume
8
ADCVU
0
ADC Left Channel Digital Volume.
FFh -> Efh: +17.625dB
EEh: +17.25dB
7:0
LADCVOL[7:0] 1100_0000
…… in steps of -0.375dB to
C0h : 0dB
BFh : -0.375dB
Beh: -0.75dB
….. in steps of -0.375dB to
02h: -71.25dB
01h: -71.625dB
00h: Digital Mute
Register 15h Left ADC Volume
PP, August 2009, Rev 3.1
w
90
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
