WM8961
Pre-Production
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The
WM8961 can be configured using the Control Interface. All registers not listed and all unused bits should not be written to.
All registers can be read back. Registers R1[15:12] returns the device ID when read.
REG
NAME
Left Input
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DEFAULT
R0 (0h)
0
0
0
0
0
0
0
IPVU LINMUTE LIZC
LINVOL[5:0]
009Fh
volume
Right Input
volume
R1 (1h)
DEVICE_ID[3:0]
CHIP_REV[2:0]
IPVU RINMUTE RIZC
RINVOL[5:0]
029Fh
LOUT1 volume
ROUT1 volume
Clocking1
R2 (2h)
R3 (3h)
R4 (4h)
R5 (5h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OUT1VU LO1ZC
OUT1VU RO1ZC
ADCDIV[2:0]
LOUT1VOL[6:0]
ROUT1VOL[6:0]
0000h
0000h
0020h
DACDIV[2:0]
MCLKDIV
0
0
ADC & DAC
Control 1
0
0
ADCPOL[1:0]
0
DACMU DEEMPH[1:0] ADCHPD 0008h
ADC & DAC
Control 2
R6 (6h)
R7 (7h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC_HPF_CUT[1:0 DACPOL[1:0]
0
DACSMMDACMR ACSLOPEAC_OSR10000h
28
Audio Interface
0
ALRSWAPBCLKINV MS DLRSWAP LRP
WL[1:0]
FORMAT[1:0] 000Ah
Clocking2
CLK_SYSC_LK_DSP_
ENA ENA
R8 (8h)
DCLKDIV[2:0]
0
BCLKDIV[3:0]
01F4h
Audio Interface
1
R9 (9h)
0
0
0
DACCOMP[1:0] ADCCOMP[1:0] OOPBACK0000h
Left DAC
volume
R10 (Ah)
R11 (Bh)
R14 (Eh)
DACVU
DACVU
LDACVOL[7:0]
RDACVOL[7:0]
00FFh
00FFh
0040h
Right DAC
volume
Audio Interface
2
LRCLK_RATE[8:0]
Software Reset
ALC1
R15 (Fh)
R17 (11h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
SW_RST_DEV_ID1[15:0]
ALCSEL[1:0]
1801h
007Bh
0000h
0032h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MAXGAIN[2:0]
ALCL[3:0]
HLD[3:0]
ATK[3:0]
ALC2
0
ALCMODE
0
0
MINGAIN[2:0]
DCY[3:0]
ALC3
Noise Gate
NGTH[4:0]
0
NGG NGAT 0000h
00C0h
Left ADC
volume
ADCVU
LADCVOL[7:0]
Right ADC
volume
R22 (16h)
R23 (17h)
R24 (18h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADCVU
TSDEN
0
RADCVOL[7:0]
00C0h
Additional
control(1)
0
0
0
0
0
0
DMONOMI
X
0
0
0
0
0
TOEN 0120h
Additional
control(2)
0
TRIS
0
0000h
Pwr Mgmt (1)
Pwr Mgmt (2)
R25 (19h)
R26 (1Ah)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VMIDSEL[1:0] VREF AINL AINR ADCL ADCR MICB
OUT1_PGOUT1_PG
0
0
0000h
0000h
DACL DACR
PKL_PGAPKR_PGA
0
0
A
A
Additional
Control (3)
R27 (1Bh)
R28 (1Ch)
R30 (1Eh)
R32 (20h)
R33 (21h)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SAMPLE_RATE[2:0]
0000h
0000h
Anti-pop
0
0
BUFIOENSOFT_ST
UFDCOPE
0
0
N
Clocking 3
MANUAL_M
005Fh
CLK_TO_DIV[1:0]
CLK_256K_DIV[5:0]
ODE
ADCL signal
path
0
0
0
0
0
0
LMICBOOST[1:0]
RMICBOOST[1:0]
0
0
0
0
0
0
0
0000h
0000h
ADCR signal
0
PP, August 2009, Rev 3.1
w
81
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
