Production Data
WM8945
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R8 (08h)
FLL_CLK_
FLL Clock Reference Divider
00 = MCLK / 1
12:11
00
FLL Control 1
REF_DIV [1:0]
01 = MCLK / 2
10 = MCLK / 4
11 = MCLK / 8
MCLK must be divided down to
<=13.5MHz.
For lower power operation, the
reference clock can be divided down
further if desired.
FLL_OUTDIV
[2:0]
FOUT clock divider
000 = 2
10:8
001
001 = 4
010 = 8
011 = 16
100 = 32
101 = 64
110 = 128
111 = 256
(FOUT = FVCO / FLL_OUTDIV)
Frequency of the FLL control block
000 = FVCO / 1 (Recommended value)
001 = FVCO / 2
FLL_CTRL_
RATE [2:0]
7:5
000
010 = FVCO / 3
011 = FVCO / 4
100 = FVCO / 5
101 = FVCO / 6
110 = FVCO / 7
111 = FVCO / 8
Recommended that this register is not
changed from default.
FLL_FRATIO
[2:0]
FVCO clock divider
4:2
000
000 = 1
001 = 2
010 = 4
011 = 8
1XX = 16
000 recommended for FREF > 1MHz
100 recommended for FREF < 16kHz
011 recommended for all other cases
Fractional enable
FLL_FRAC
1
1
0 = Integer Mode
1 = Fractional Mode
Integer mode offers reduced power
consumption. Fractional mode offers
best FLL performance, provided also
that N.K is a non-integer value.
FLL_ENA
FLL Enable
0 = Disabled
1 = Enabled
0
0
PD, May 2011, Rev 4.1
77
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
