Production Data
WM8945
EXAMPLE FLL SETTINGS
Table 54 provides example FLL settings for generating common SYSCLK frequencies from a variety
of low and high frequency reference inputs.
FREF
FOUT
FLL_CLK_
REF_DIV
FVCO
FLL_N
FLL_K
FLL_
FRATIO
FLL_
OUTDIV
FLL_
FRAC
8.000
kHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
705
0.6
16
4
1
(2C1h)
768
(9999h)
0.0
(4h)
16
(4h)
8
(1h)
4
8.000
kHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
(300h)
344
(0000h)
0.53125
(8800h)
0.0
(1h)
4
32.768
kHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(158h)
375
(3h)
8
(1h)
4
32.768
kHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(177h)
14
(0000h)
0.7
(3h)
8
(1h)
4
768.000
kHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(00Eh)
16
(B333h)
0.0
(3h)
8
(1h)
4
768.000
kHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(010h)
88
(0000h)
0.2
(3h)
1
(1h)
4
1.024
MHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(058h)
96
(3333h)
0.0
(0h)
1
(1h)
4
1.024
MHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(060h)
14
(0000h)
0.7
(0h)
1
(1h)
4
6.144
MHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(00Eh)
16
(B333h)
0.0
(0h)
1
(1h)
4
6.144
MHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(010h)
8
(0000h)
0.0
(0h)
1
(1h)
4
11.2896
MHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(008h)
8
(0000h)
0.70749
(B51Eh)
0.5264
(86C2h)
0.192
(0h)
1
(1h)
4
11.2896
MHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(008h)
7
(0h)
1
(1h)
4
12.000
MHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(007h)
8
(0h)
1
(1h)
4
12.000
MHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(008h)
7
(3127h)
0.35
(0h)
1
(1h)
4
12.288
MHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(007h)
8
(599Ah)
0.0
(0h)
1
(1h)
4
12.288
MHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(008h)
6
(0000h)
0.94745
(F28Ch)
0.56185
(8FD5h)
0.408
(0h)
1
(1h)
4
13.000
MHz
22.5792
MHz
divide by 1
(0h)
90.3168
MHz
(006h)
7
(0h)
1
(1h)
4
13.000
MHz
24.576
MHz
divide by 1
(0h)
98.304
MHz
(007h)
9
(0h)
1
(1h)
4
19.200
MHz
22.5792
MHz
divide by 2
(1h)
90.3168
MHz
(009h)
10
(6873h)
0.24
(0h)
1
(1h)
4
19.200
MHz
24.576
MHz
divide by 2
(1h)
98.304
MHz
(00Ah)
6
(3D71h)
0.69013
(B0Adh)
0.28178
(4823h)
(0h)
1
(1h)
4
27.000
MHz
22.5792
MHz
divide by 2
(1h)
90.3168
MHz
(006h)
7
(0h)
1
(1h)
4
27.000
MHz
24.576
MHz
divide by 2
(1h)
98.304
MHz
(007h)
(0h)
(1h)
Table 54 Example FLL Settings
PD, May 2011, Rev 4.1
79
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
