WM8945
Production Data
DESCRIPTION
Oscillator Enable
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R6 (06h)
15
OSC_CLK_ENA
0
Clock Gen
control
0 = Disabled
1 = Enabled
This needs to be set when doing
AUXADC measurements, or when a
timeout clock is required for PGA
zero cross or GPIO input detection
MCLK_PULL
[1:0]
MCLK pull-up / pull-down Enable
00 = no pull-up or pull-down
01 = pull-down
14:13
00
10 = pull-up
11 = reserved
CLKOUT_SEL
CLKOUT Source Select
0 = SYSCLK
12
0
1 = FLL or MCLK (set by
SYSCLK_SRC register)
CLKOUT_DIV
[1:0]
CLKOUT Clock divider
00 = divide by 1
01 = divide by 2
10 = divide by 4
11 = divide by 8
SYSCLK Enable
0 = Disabled
11:10
00
SYSCLK_ENA
SYSCLK_SRC
9
8
0
0
1 = Enabled
SYSCLK Source Select
0 = MCLK
1 = FLL output
SYSCLK_DIV
[2:0]
000
SYSCLK Clock divider
(Sets the scaling for either the
MCLK or FLL clock output,
depending on SYSCLK_SRC)
000 = divide by 1
7:5
001 = divide by 1.5
010 = divide by 2
011 = divide by 3
100 = divide by 4
101 = divide by 6
110 = divide by 8
111 = divide by 12
TOCLK_ENA
TOCLK Enabled
4
0
(Enables timeout clock for GPIO
level detection, AMU, and PGA zero
cross timeout)
0 = Disabled
1 = Enabled
R7 (07h)
SR [3:0]
Audio Sample Rate select
0011 = 8kHz
3:0
1101
Additional
control
0100 = 11.025kHz
0101 = 12kHz
0111 = 16kHz
1000 = 22.05kHz
1001 = 24kHz
1011 = 32kHz
1100 = 44.1kHz
1101 = 48kHz
Table 49 Clocking and Sample Rate Control
PD, May 2011, Rev 4.1
74
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
