WM8945
Production Data
DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
R9 (09h)
15:0
FLL_K[15:0]
3137h
Fractional multiply for FREF
(MSB = 0.5)
FLL Control 2
R10 (0Ah)
FLL_N[9:0]
Integer multiply for FREF
(LSB = 1)
14:5
3:0
008h
0100
FLL Control 3
FLL_GAIN
[3:0]
Gain applied to error
0000 = x 1 (Recommended value)
0001 = x 2
0010 = x 4
0011 = x 8
0100 = x 16
0101 = x 32
0110 = x 64
0111 = x 128
1000 = x 256
Recommended that this register is set
0000.
Table 53 Frequency Locked Loop Control
EXAMPLE FLL CALCULATION
To generate 24.576MHz output (FOUT) from a 12.000MHz reference clock (FREF):
Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:
FLL_CLK_REF_DIV = 00 (divide by 1)
Set FLL_CTRL_RATE to the recommended setting:
FLL_CTRL_RATE = 000 (divide by 1)
Sett FLL_GAIN to the recommended setting:
FLL_GAIN = 0000 (multiply by 1)
Set FLL_OUTDIV for the required output frequency as shown in Table 51:-
FOUT = 24.576MHz, therefore FLL_OUTDIV = 1h (divide by 4)
Set FLL_FRATIO for the given reference frequency as shown in Table 52:
REF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)
F
Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:-
VCO = 24.576 x 4 = 98.304MHz
F
Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):
N.K = 98.304 / (1 x 12) = 8.192
Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-
FLL_N is 8(dec) = 008(hex). FLL_K is 0.192 (dec) = 3127(hex).
Confirm that N.K is a fractional quantity and set FLL_FRAC:
N.K is fractional. Set FLL_FRAC = 1.
Note that, if N.K is an integer, then an alternative value of FLL_FRATIO may be selected in
order to produce a fractional value of N.K.
PD, May 2011, Rev 4.1
78
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
