Production Data
WM8945
SYSCLK may be derived either from MCLK or from the FLL; this is selected using the SYSCLK_SRC
register bit. SYSCLK is enabled using the SYSCLK_ENA and may be modified using a programmable
divider configured by SYSCLK_DIV. It is important that SYSCLK_DIV is correctly set in order to
produce 512 x fs at its output, where fs is the audio sampling rate.
The sampling rate for the CODEC and Digital Audio Interface is configured using the SR register field.
In Master mode, the frequency of the Left/Right Clock output on the LRCLK pin is the BCLK
frequency divided by 64 producing 32 BCLK cycles per channel. In Master mode, the BCLK_DIV
register configures the bit clock frequency output on BCLK.
The WM8945 can output a configurable clock on the GPIO pins; this is enabled automatically
whenever a GPIO pin is configured for CLKOUT output. The source can either be before or after the
SYSCLK divider, as shown in Figure 31. The source is selected using CLKOUT_SEL, and may be
modified using a programmable divider configured by CLKOUT_DIV.
The WM8945 free-running oscillator required for AUXADC, Touch Panel, GPIO input de-bounced and
Interrupt functions must be enabled using OSC_CLK_ENA whenever any of these functions is
required.
The zero-cross facility on input and output PGAs requires a timeout clock. This is enabled using the
TOCLK_ENA bit. The oscillator must also be enabled using OSC_CLK_ENA.
PD, May 2011, Rev 4.1
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