Production Data
WM8945
DIGITAL MIC CLOCKING
When any GPIO is configured as DMICCLK output, the WM8945 outputs a clock which supports
Digital Mic operation at the ADC sampling rate. Although the ADC is not used, the SYSCLK and
Sample Rate control fields must still be set as they would for ADC operation.
The clock frequencies for each of the sample rates is shown in Table 50
PCM SAMPLE RATE
8kHz
DMICCLK
1.024MHz
1.411MHz
1.536MHz
2.048MHz
2.8224MHz
3.072MHz
2.048MHz
2.8224MHz
3.072MHz
FS RATE
128fs
128fs
128fs
128fs
128fs
128fs
64fs
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
64fs
64fs
Table 50 Digital Microphone Clock Frequencies
FREQUENCY LOCKED LOOP (FLL)
The integrated FLL can be used to generate SYSCLK from a wide variety of different reference
sources and frequencies. The FLL uses MCLK as its reference, which may be a high frequency (e.g.
12.288MHz) or low frequency (e.g. 32,768kHz) reference. The FLL is tolerant of jitter and may be
used to generate a stable SYSCLK from a less stable input signal. The FLL characteristics are
summarised in “Electrical Characteristics”.
The FLL is enabled using the FLL_ENA register bit. At initial power on the VMID voltage must be
allowed to settle at its final vale before enabling the FLL. Note that, when changing FLL settings, it is
recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other
register settings have been updated. When changing the input reference frequency FREF, it is
recommended that the FLL be reset by setting FLL_ENA to 0.
The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK) by 1, 2, 4 or 8.
This field should be set to bring the reference down to 13.5MHz or below. For best performance, it is
recommended that the highest possible frequency – within the 13.5MHz limit – should be selected.
The field FLL_CTRL_RATE controls internal functions within the FLL; it is recommended that only the
default setting be used for this parameter. FLL_GAIN controls the internal loop gain and should be set
to the recommended value.
The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real
number represented by FLL_N and FLL_K. The field FLL_N is an integer (LSB = 1); FLL_K is the
fractional portion of the number (MSB = 0.5). The fractional portion is only valid when enabled by the
field FLL_FRAC.
Power consumption in the FLL is reduced in integer mode; however, the performance may also be
reduced, with increased noise or jitter on the output.
If low power consumption is required, then FLL settings must be chosen where N.K is an integer (i.e.
FLL_K = 0). In this case, the fractional mode can be disabled by setting FLL_FRAC = 0.
For best FLL performance, a non-integer value of N.K is required. In this case, the fractional mode
must be enabled by setting FLL_FRAC = 1. The FLL settings must be adjusted, if necessary, to
produce a non-integer value of N.K.
The FLL output frequency is generated according to the following equation:
FOUT = (FVCO / FLL_OUTDIV)
PD, May 2011, Rev 4.1
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
