Pre-Production
WM8904
A list of possible TOCLK rates is provided in Table 66.
TOCLK
TOCLK_RATE
TOCLK_RATE_X4
TOCLK_RATE_DIV16
FREQ (Hz)
PERIOD
(ms)
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1000
500
1
2
0
1
250
4
0
125
8
1
62.5
16
32
64
128
0
31.25
15.625
7.8125
1
0
Table 66 TOCLK Rates
ADC / DAC OPERATION AT 88.2K / 96K
The WM8904 supports ADC or DAC operation at 88.2kHz and 96kHz sample rates. This section
details specific conditions applicable to these operating modes. Note that simultaneous ADC and
DAC operation at 88.2kHz or 96kHz is not possible.
For DAC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 67. DAC operation at these sample rates is achieved by setting the SAMPLE_RATE
field to half the required sample rate (eg. select 48kHz for 96kHz mode).
For DAC operation at 88.2kHz or 96kHz sample rates, the ADCs must both be disabled (ADCL_ENA
= 0 and ADCR_ENA = 0). Also, the DAC_OSR128 register must be set to 0. ReTuneTM Mobile can
not be used during 88.2kHz or 96kHz operation, so EQ_ENA must be set to 0.
The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the
“Signal Timing Requirements” section.
SAMPLE RATE
REGISTER CONFIGURATION
SAMPLE_RATE = 101
CLOCKING RATIO
88.2kHz
SYSCLK = 128 x fs
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
SAMPLE_RATE = 101
96kHz
SYSCLK = 128 x fs
CLK_SYS_RATE = 0001 (SYSCLK / fs = 128)
BCLK_DIV = 00010
LRCLK_RATE = 040h
Table 67 DAC Operation at 88.2kHz and 96kHz Sample Rates
For ADC operation at 88.2kHz or 96kHz sample rates, the available clocking configurations are
detailed in Table 68.
ADC operation at these sample rates is achieved by setting the SAMPLE_RATE field to half the
required sample rate (eg. select 48kHz for 96kHz mode). For ADC operation at 88.2kHz or 96kHz
sample rates, the DACs must both be disabled (DACL_ENA = 0 and DACR_ENA = 0). Note that
ADC_OSR128, ADC_128_OSR_TST_MODE, and ADC_BIASX1P5 must be configured according to
Table 68.
The SYSCLK frequency is derived from MCLK. The maximum MCLK frequency is defined in the
“Signal Timing Requirements” section.
PP, Rev 3.3, September 2012
107
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