WM8904
Pre-Production
OPCLK CONTROL
A clock output (OPCLK) derived from SYSCLK may be output on a GPIO pin. This clock is enabled
by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.
This output of this clock is also dependent upon the GPIO register settings described under “General
Purpose Input/Output (GPIO)”.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R22 (16h)
GPIO Clock Output Enable
0 = disabled
3
OPCLK_ENA
0
Clock Rates 2
1 = enabled
R26 (1Ah)
GPIO Output Clock Divider
0000 = SYSCLK
11:8
OPCLK_DIV [3:0]
0000
Audio
Interface 2
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
Table 64 OPCLK Control
TOCLK CONTROL
A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input de-
bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,
and its frequency is controlled by TOCLK_RATE and TOCLK_RATE_X4, as described in Table 65.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R22 (16h)
TOCLK Rate Divider (/2)
0 = f / 2
12
TOCLK_RATE
0
Clock Rates 2
1 = f / 1
Zero Cross timeout enable
0 = Disabled
0
TOCLK_ENA
0
0
0
1 = Enabled
R20 (14h)
Clock Rates 0
TOCLK Rate Divider (/16)
0 = f / 1
14
13
TOCLK_RATE_
DIV16
1 = f / 16
TOCLK Rate Multiplier
0 = f x 1
TOCLK_RATE_
X4
1 = f x 4
Table 65 TOCLK Control
PP, Rev 3.3, September 2012
106
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
